Q1ASM User guide

Q1ASM is an assembly language used to program the sequencers. A user guide for how to use the sequencer can be found here.

Assembly syntax

An assembly source file consists of a sequence of lines. Each line contains a directive or a code instruction (optionally followed by a comment), or a comment.

• Case Sensitivity: The entire syntax is case-sensitive.

• Comments: Begin with a hash symbol (#). The assembler ignores all comments.

Directives

The .DEF directive creates a user-defined alias. .DEF <name> <value> allows you to assign a symbolic <name> to a <value>.

• <name>: Starts with a letter (cannot start with a number). Consists of uppercase/lowercase letters and/or numbers.

• <value>: The string literal that will replace <name>. Can be any string (e.g., 42, R63).

Code

A source line has the following format:

[label:] instruction argument,argument,... [comment]

Fields are separated by whitespace (spaces or tabs). Operands may also be separated by whitespace.

Arguments

Q1ASM instructions use the following types of arguments:

Type	Acronym	Format	Description
Immediate	I	#	32-bit decimal or hexadecimal value (e.g. 1000, -42, 0x3a)
Register	R	R#	Register address in range 0 to 63 (e.g. R0), containing a 32-bit value.

Labels

Labels are used to mark addresses for program flow control (e.g., for jumps and loops). A label is defined by placing an identifier followed by a colon :. e.g. mylabel:

• Any instruction can be preceded by a label.

• Labels can be placed on a separate line (See the Q1 core section for an example).

Label references

A label is referenced by placing an at-symbol @ followed by the label’s name. e.g. mylabel: is referred as @mylabel.

• A label reference has to be an immediate argument.

• Forward references are allowed, meaning you can refer to a label before it is defined.

Alias references

An alias is referenced by placing a dollar sign $ followed by the alias’s name.

Tip

Example

.DEF                SQG_TIME                100         # Time in ns for single qubit gate

wait                $SQG_TIME

• An alias reference can be immediate or register argument.

• Forward references are not allowed; the .DEF must appear before the alias is used.

Instructions

A sequencer consists of the Q1 core and the real-time (RT) core. The Q1 core pushes instructions to a queue, which are then executed by the RT core. See Q1 instructions and RT instructions for more specific instructions.

The total duration of an experiment, or its wall-time, is determined only by the duration argument of RT instructions. The Q1 core’s processing time is only relevant if it cannot prepare instructions fast enough to keep the RT core busy.

If the RT queue runs empty, the sequencer will halt and raise an error.

In the tables below, the arguments of an instruction are specified as arg0_name: type. An instruction may have multiple allowed combinations of arguments, which are specified on separate lines.

Q1 Instructions

Core Instructions

illegal

variants

signature	illegal
arguments	N/A
Q1 core runtime	4

Description

An invalid instruction. If executed, the sequencer halts with an error.

Note

This may be used to debug your sequencer but is typically unused.

Q1 Core actions

• Halt

• Set sequencer status to STOPPED

• Set error flag SEQUENCE_PROCESSOR_RT_EXEC_ILLEGAL_INSTRUCTION

RT Core actions

• Halt

stop

variants

signature	stop status: R
arguments	status R0 to R63
Q1 core runtime	4

signature	stop status: I
arguments	status \([-2^{31}, 2^{31}-1]\)
Q1 core runtime	4

signature	stop
arguments	N/A
Q1 core runtime	4

Description

Stops the sequencer with a stop code (arg0). If no argument is provided, the default stop code is 0.

Q1 Core actions

• Stop

• Set sequencer status to Q1_STOPPED

RT Core actions

• Disable underflow error

• Once RT queue is empty, set sequencer status to STOPPED

nop

variants

signature	nop
arguments	N/A
Q1 core runtime	4

Description

No operation. Does nothing for one Q1 core clock cycle (4ns).

Tip

This instruction is mainly used if the Q1 core needs to wait 1 clock cycle for a register to be written to. Some ALU instructions (like add and sub) move on to the next Q1 core instruction in 12 ns, but require one extra cycle to be able to retrieve the result from the destination register. The nop instruction may be used for this.

Q1 Core actions

• Wait 1 clock cycle (4 ns)

Jump Instructions

For jump instructions, the immediate is generally a label, representing the instruction address of the following instruction. The functionality of jumping to addresses stored in registers can be used for creating subroutines, to add offsets to labels, writing case tables, and so on.

jmp

Unconditional Jump

variants

signature	jmp address: R
arguments	address R0 to R63
Q1 core runtime	16 on jump, 4 on continue

signature	jmp address: I
arguments	address \([0, 2^{14}-1]\)
Q1 core runtime	16 on jump, 4 on continue

Description

Q1 Core actions

• Jump to address.

jz

Jump if zero (a.k.a) Jump if equal

variants

signature	jz address: R
arguments	address R0 to R63
Q1 core runtime	16 on jump, 4 on continue

signature	jz address: I
arguments	address \([0, 2^{14}-1]\)
Q1 core runtime	16 on jump, 4 on continue

Description

When comparing two numbers (cmp a, b), jump if a==b.

Q1 Core actions

• Jump to address if the zero_flag == 1.

Note

The flags zero_flag, overflow_flag, carry_flag and negative_flag are set by many ALU instructions.

For example, cmp R0, 6 would set zero_flag = 1 if R0==6.

jnz

Jump if not zero (a.k.a) Jump if not equal

variants

signature	jnz address: R
arguments	address R0 to R63
Q1 core runtime	16 on jump, 4 on continue

signature	jnz address: I
arguments	address \([0, 2^{14}-1]\)
Q1 core runtime	16 on jump, 4 on continue

Description

When comparing two numbers (cmp a, b), jump if a!=b.

Q1 Core actions

Jump to address if the zero_flag == 0.

Note

The flags zero_flag, overflow_flag, carry_flag and negative_flag are set by many ALU instructions.

For example, cmp R0, 6 would set zero_flag = 0 if R0!=6.

jo

Jump if overflow

variants

signature	jo address: R
arguments	address R0 to R63
Q1 core runtime	16 on jump, 4 on continue

signature	jo address: I
arguments	address \([0, 2^{14}-1]\)
Q1 core runtime	16 on jump, 4 on continue

Description

Jump if the previous ALU operation had an overflow.

Q1 Core actions

Jump to address if the overflow_flag == 1.

Note

The flags zero_flag, overflow_flag, carry_flag and negative_flag are set by many ALU instructions.

For example, cmp R0, {2**31 - 6} would set overflow_flag = 1 if R0==10.

jno

Jump if not overflow

variants

signature	jno address: R
arguments	address R0 to R63
Q1 core runtime	16 on jump, 4 on continue

signature	jno address: I
arguments	address \([0, 2^{14}-1]\)
Q1 core runtime	16 on jump, 4 on continue

Description

Jump if the previous ALU operation did not have an overflow.

Q1 Core actions

Jump to address if the overflow_flag == 0.

Note

The flags zero_flag, overflow_flag, carry_flag and negative_flag are set by many ALU instructions.

For example, cmp R0, {2**31 - 6} would set overflow_flag = 0 if R0==4.

js

Jump if negative (a.k.a Jump if the sign-bit is 1)

variants

signature	js address: R
arguments	address R0 to R63
Q1 core runtime	16 on jump, 4 on continue

signature	js address: I
arguments	address \([0, 2^{14}-1]\)
Q1 core runtime	16 on jump, 4 on continue

Description

When comparing two numbers (cmp a, b), jump if a - b < 0.

Note

The js instruction is very similar to jl but is not the same. Consider the case when a=-2**31 and b=2**31. Mathematically, a-b = -2**32 which cannot be represented as a 32 bit signed integer.

The js instruction will still jump since the result is negative. jl will not jump because it cannot be represented in 32 bits.

Q1 Core actions

Jump to address if the negative_flag == 1.

Note

The flags zero_flag, overflow_flag, carry_flag and negative_flag are set by many ALU instructions.

For example, cmp R0, 5 would set negative_flag = 1 if R0==4.

jns

Jump if not negative (a.k.a Jump if the sign-bit is 0)

variants

signature	jns address: R
arguments	address R0 to R63
Q1 core runtime	16 on jump, 4 on continue

signature	jns address: I
arguments	address \([0, 2^{14}-1]\)
Q1 core runtime	16 on jump, 4 on continue

Description

When comparing two numbers (cmp a, b), jump if a - b >= 0.

Note

The jns instruction is very similar to jge but is not the same. Consider the case when a=2**31 and b=-2**31. Mathematically, a-b = 2**32 which cannot be represented as a 32 bit signed integer.

The jns instruction will still jump since the sign bit is not set. jge will not jump because it cannot be represented in 32 bits.

Q1 Core actions

Jump to address if the negative_flag == 0.

Note

The flags zero_flag, overflow_flag, carry_flag and negative_flag are set by many ALU instructions.

For example, cmp R0, 5 would set negative_flag = 0 if R0==6.

jg

Jump if greater than

variants

signature	jg address: R
arguments	address R0 to R63
Q1 core runtime	16 on jump, 4 on continue

signature	jg address: I
arguments	address \([0, 2^{14}-1]\)
Q1 core runtime	16 on jump, 4 on continue

Description

When comparing signed numbers (cmp a, b), jump if a>b.

Q1 Core actions

Jump to address if the zero_flag == 0 and negative_flag == overflow_flag.

Note

The flags zero_flag, overflow_flag, carry_flag and negative_flag are set by many ALU instructions.

For example, cmp R0, 5 would set zero_flag = 0, negative_flag = 0 and overflow_flag = 0 if R0==6.

jge

Jump if greater than or equal to

variants

signature	jge a: R , rgt: I , address: R
arguments	a R0 to R63 rgt \([0, 2^{32}-1]\) address R0 to R63
Q1 core runtime	24 on jump, 4 on continue

signature	jge a: R , rgt: I , address: I
arguments	a R0 to R63 rgt \([0, 2^{32}-1]\) address \([0, 2^{14}-1]\)
Q1 core runtime	24 on jump, 4 on continue

signature	jge address: R
arguments	address R0 to R63
Q1 core runtime	24 on jump, 4 on continue

signature	jge address: I
arguments	address \([0, 2^{14}-1]\)
Q1 core runtime	24 on jump, 4 on continue

Description

When comparing signed numbers (cmp a, b), jump if a>=b.

Important

The variants jge a,b,address and jge R,I,I are deprecated in favor of the new type of jump instructions that make use of the ALU flags. They are included here for backwards compatibility and compare unsigned numbers, and jump if a>=b. Additionally, these variants are broken up into two instructions in instruction memory into a cmp R,I and jge R/I.

Note

The jns instruction is very similar to jge but is not the same. Consider the case when a=2**31 and b=-2**31. Mathematically, a-b = 2**32 which cannot be represented as a 32 bit signed integer.

The jns instruction will still jump since the sign bit is not set. jge will not jump because it cannot be represented in 32 bits.

Q1 Core actions

Jump to address if the zero_flag == 0 and negative_flag == overflow_flag.

Note

The flags zero_flag, overflow_flag, carry_flag and negative_flag are set by many ALU instructions.

For example, cmp R0, 5 would set zero_flag = 0, negative_flag = 0 and overflow_flag = 0 if R0==6.

jl

Jump if less than

variants

signature	jl address: R
arguments	address R0 to R63
Q1 core runtime	16 on jump, 4 on continue

signature	jl address: I
arguments	address \([0, 2^{14}-1]\)
Q1 core runtime	16 on jump, 4 on continue

Description

When comparing signed numbers (cmp a, b), jump if a<b.

Note

The js instruction is very similar to jl but is not the same. Consider the case when a=-2**31 and b=2**31. Mathematically, a-b = -2**32 which cannot be represented as a 32 bit signed integer.

The js instruction will still jump since the result is negative. jl will not jump because it cannot be represented in 32 bits.

Q1 Core actions

Jump to address if the negative_flag != overflow_flag.

Note

The flags zero_flag, overflow_flag, carry_flag and negative_flag are set by many ALU instructions.

For example, cmp R0, 5 would set zero_flag = 0, negative_flag = 1 and overflow_flag = 0 if R0==4.

jlt

Jump if less than

variants

signature	jlt a: R , rgt: I , address: R
arguments	a R0 to R63 rgt \([0, 2^{32}-1]\) address R0 to R63
Q1 core runtime	24 on jump, 4 on continue

signature	jlt a: R , rgt: I , address: I
arguments	a R0 to R63 rgt \([0, 2^{32}-1]\) address \([0, 2^{14}-1]\)
Q1 core runtime	24 on jump, 4 on continue

Description

When comparing unsigned numbers (cmp a, b), jump if a<b.

Important

This instruction is deprecated in favor of the new type of jump instructions that make use of the ALU flags. Additionally, the instruction is broken up into two instructions in instruction memory into a cmp a,b and jb address.

jle

Jump if less than or equal to

variants

signature	jle address: R
arguments	address R0 to R63
Q1 core runtime	16 on jump, 4 on continue

signature	jle address: I
arguments	address \([0, 2^{14}-1]\)
Q1 core runtime	16 on jump, 4 on continue

Description

When comparing signed numbers (cmp a, b), jump if a<=b.

Note

The js instruction is very similar to jl but is not the same. Consider the case when a=-2**31 and b=2**31. Mathematically, a-b = -2**32 which cannot be represented as a 32 bit signed integer.

The js instruction will still jump since the result is negative. jl will not jump because it cannot be represented in 32 bits.

Q1 Core actions

Jump to address if the zero_flag == 1 or negative_flag != overflow_flag.

Note

The flags zero_flag, overflow_flag, carry_flag and negative_flag are set by many ALU instructions.

For example, cmp R0, 5 would set zero_flag = 0, negative_flag = 1 and overflow_flag = 0 if R0==4.

ja

Jump if above

variants

signature	ja address: R
arguments	address R0 to R63
Q1 core runtime	16 on jump, 4 on continue

signature	ja address: I
arguments	address \([0, 2^{14}-1]\)
Q1 core runtime	16 on jump, 4 on continue

Description

When comparing unsigned numbers (cmp a, b), jump if a>b.

Q1 Core actions

Jump to address if the zero_flag == 0 and carry_flag == 0.

Note

The flags zero_flag, overflow_flag, carry_flag and negative_flag are set by many ALU instructions.

For example, cmp R0, 5 would set zero_flag = 0, carry_flag == 0 if R0==6.

jae

Jump if above or equal to

variants

signature	jae address: R
arguments	address R0 to R63
Q1 core runtime	16 on jump, 4 on continue

signature	jae address: I
arguments	address \([0, 2^{14}-1]\)
Q1 core runtime	16 on jump, 4 on continue

Description

When comparing unsigned numbers (cmp a, b), jump if a>=b.

Q1 Core actions

Jump to address if the carry_flag == 0.

Note

The flags zero_flag, overflow_flag, carry_flag and negative_flag are set by many ALU instructions.

For example, cmp R0, 5 would set carry_flag == 0 if R0==6.

jb

Jump if below

variants

signature	jb address: R
arguments	address R0 to R63
Q1 core runtime	16 on jump, 4 on continue

signature	jb address: I
arguments	address \([0, 2^{14}-1]\)
Q1 core runtime	16 on jump, 4 on continue

Description

When comparing unsigned numbers (cmp a, b), jump if a<b.

Q1 Core actions

Jump to address if the carry_flag == 1.

Note

The flags zero_flag, overflow_flag, carry_flag and negative_flag are set by many ALU instructions.

For example, cmp R0, 5 would set carry_flag == 1 if R0==4.

jbe

Jump if below or equal to

variants

signature	jbe address: R
arguments	address R0 to R63
Q1 core runtime	16 on jump, 4 on continue

signature	jbe address: I
arguments	address \([0, 2^{14}-1]\)
Q1 core runtime	16 on jump, 4 on continue

Description

When comparing unsigned numbers (cmp a, b), jump if a<=b.

Q1 Core actions

Jump to address if the zero_flag == 1 or carry_flag == 1.

Note

The flags zero_flag, overflow_flag, carry_flag and negative_flag are set by many ALU instructions.

For example, cmp R0, 5 would set zero_flag = 0, carry_flag == 1 if R0==4.

loop

variants

signature	loop source: R , address: R
arguments	source R0 to R63 address R0 to R63
Q1 core runtime	24 on jump, 4 on continue

signature	loop source: R , address: I
arguments	source R0 to R63 address \([0, 2^{14}-1]\)
Q1 core runtime	24 on jump, 4 on continue

Description

Subtract 1 from source. If the result is 0, jump to address.

Important

This instruction is deprecated in favor of the new type of jump instructions that make use of the ALU flags. Additionally, the instruction is broken up into two instructions in instruction memory into a sub a,1,a and jnz address.

Arithmetic Instructions

A short note on 2’s complement arithmetic

The Q1 processor uses 32 bit registers. These 32 bits can each have a value of 0 or 1, and can represent a total of \(2^{32}\) numbers.

When an instruction interprets a register as an unsigned 32 bit integer (uint32), the range of numbers that can be represented is [\(0\), \(2^{32} - 1\)]. Examples of instructions that interpret registers as unsigned integers are lsr, upd_param.

When an instruction interprets a register as an signed 32 bit integer (int32), the range of numbers that can be represented is [\(-2^{31}\), \(2^{31} - 1\)]. Examples of instructions that interpret registers as signed integers are asr, set_freq.

This is why the full range of immediates for instructions is [\(-2^{31}\), \(2^{32} - 1\)].

For many arithmetic instructions, it does not matter whether the 32 bits are representing a signed or an unsigned number. The operation that needs to be performed is mathematically identical. However, the interpretation of the flags that are set may differ after the arithmetic operation. An example is the add instruction. See the example below using only 3 bits for why that is the case.

3 bits can represent signed numbers from -4 to 3 and unsigned numbers from 0 to 7.

Decimal	Signed binary	Unsigned binary
7	-	111
6	-	110
5	-	101
4	-	100
3	011	011
2	010	010
1	001	001
0	000	000
-1	111	-
-2	110	-
-3	101	-
-4	100	-

Now, let’s perform an add of 110 + 011.

Note that additions for unsigned integers and signed integers are both performed at the same time:

• The 3 bit result register in both cases stores 001. In the signed register case, this is directly the result.

• In the unsigned integer case, you have to add another bit called the carry_flag as the MSB. Then the result is 1001 which is the unsigned integer representation of 9 which cannot be represented with 3 bits.

move

Move/copy source to destination

variants

signature	move source: R , dst: R
arguments	source R0 to R63 dst R0 to R63
Q1 core runtime	4

signature	move source: I , dst: R
arguments	source \([-2^{31}, 2^{32}-1]\) dst R0 to R63
Q1 core runtime	4

Description

Move or copy the source to the destination register.

Q1 Core actions

• destination = source

ALU flags

The ALU flags are unchanged for this instruction.

not

Bitwise invert

variants

signature	not source: R , dst: R
arguments	source R0 to R63 dst R0 to R63
Q1 core runtime	12

signature	not source: I , dst: R
arguments	source \([-2^{31}, 2^{32}-1]\) dst R0 to R63
Q1 core runtime	12

Description

Bitwise invert the source and move the result to the destination.

Q1 Core actions

• destination = ~source

ALU flags

• ZF: Set if result is zero.

• NF: Set if result is negative.

• CF: 0.

• OF: 0.

add

Addition

variants

signature	add a: R , b: R , dst: R
arguments	a R0 to R63 b R0 to R63 dst R0 to R63
Q1 core runtime	12

signature	add a: R , b: I , dst: R
arguments	a R0 to R63 b \([-2^{31}, 2^{32}-1]\) dst R0 to R63
Q1 core runtime	12

signature	add b: I , a: R , dst: R
arguments	b \([-2^{31}, 2^{32}-1]\) a R0 to R63 dst R0 to R63
Q1 core runtime	12

Description

Add b to a and move the result to destination.

Q1 Core actions

• destination = a + b

ALU flags

• ZF: Set if result is zero.

• NF: Set if result is negative.

• CF: Set if \(a + b > 2^{32}-1\) (unsigned carry).

• OF: Set if signed overflow occurs (result exceeds signed 32-bit range).

sub

Subtraction

variants

signature	sub a: R , b: R , dst: R
arguments	a R0 to R63 b R0 to R63 dst R0 to R63
Q1 core runtime	12

signature	sub a: R , b: I , dst: R
arguments	a R0 to R63 b \([-2^{31}, 2^{32}-1]\) dst R0 to R63
Q1 core runtime	12

signature	sub b: I , a: R , dst: R
arguments	b \([-2^{31}, 2^{32}-1]\) a R0 to R63 dst R0 to R63
Q1 core runtime	12

Description

Subtract b from a and move the result to destination.

Q1 Core actions

• destination = a - b

ALU flags

• ZF: Set if result is zero.

• NF: Set if result is negative.

• CF: Set if borrow is required (\(a < b\) unsigned).

• OF: Set if signed overflow occurs.

cmp

Compare

variants

signature	cmp a: R , b: R
arguments	a R0 to R63 b R0 to R63
Q1 core runtime	12

signature	cmp a: R , b: I
arguments	a R0 to R63 b \([-2^{31}, 2^{32}-1]\)
Q1 core runtime	12

signature	cmp b: I , a: R
arguments	b \([-2^{31}, 2^{32}-1]\) a R0 to R63
Q1 core runtime	12

Description

Compare a and b by performing a subtraction without storing the result. Used to set ALU flags for jump instructions.

Note

For example, cmp 4, R0 followed by jz @address can be used to jump to an address if R0 == 4.

Q1 Core actions

• a - b (result discarded)

ALU flags

• Same as sub.

mulu16

Unsigned 16-bit Multiply

variants

signature	mulu16 a: R , b: R , dst: R
arguments	a R0 to R63 b R0 to R63 dst R0 to R63
Q1 core runtime	12

signature	mulu16 a: R , rgt: I , dst: R
arguments	a R0 to R63 rgt \([0, 2^{16}-1]\) dst R0 to R63
Q1 core runtime	12

signature	mulu16 rgt: I , a: R , dst: R
arguments	rgt \([0, 2^{16}-1]\) a R0 to R63 dst R0 to R63
Q1 core runtime	12

Description

Multiply two unsigned 16-bit integers and move the 32-bit result to destination.

Note

16-bit unsigned integers range from \([0, 2^{16} - 1]\). If a register has a number not in the range, then it will just use the least significant 16 bits.

Q1 Core actions

• destination = a * b (Unsigned)

ALU flags

• ZF: Set if result is zero.

• NF: Set if result is negative.

• CF: 0.

• OF: 0.

muls16

Signed 16-bit Multiply

variants

signature	muls16 a: R , b: R , dst: R
arguments	a R0 to R63 b R0 to R63 dst R0 to R63
Q1 core runtime	12

signature	muls16 a: R , rgt: I , dst: R
arguments	a R0 to R63 rgt \([-2^{15}, 2^{15}-1]\) dst R0 to R63
Q1 core runtime	12

signature	muls16 rgt: I , a: R , dst: R
arguments	rgt \([-2^{15}, 2^{15}-1]\) a R0 to R63 dst R0 to R63
Q1 core runtime	12

Description

Multiply two signed 16-bit integers a and b and move the signed 32-bit result to destination.

Note

16-bit signed integers range from [\(-2^{15}, 2^{15} - 1\)]. If a register has a number not in the range, then it will just use the least significant 16 bits.

Q1 Core actions

• destination = a * b (Signed)

ALU flags

• ZF: Set if result is zero.

• NF: Set if result is negative.

• CF: 0.

• OF: 0.

mulu32l

Unsigned 32-bit Multiply Low

variants

signature	mulu32l a: R , b: R , dst: R
arguments	a R0 to R63 b R0 to R63 dst R0 to R63
Q1 core runtime	20

signature	mulu32l a: R , rgt: I , dst: R
arguments	a R0 to R63 rgt \([0, 2^{32}-1]\) dst R0 to R63
Q1 core runtime	20

signature	mulu32l rgt: I , a: R , dst: R
arguments	rgt \([0, 2^{32}-1]\) a R0 to R63 dst R0 to R63
Q1 core runtime	20

Description

Multiply two unsigned 32-bit integers a and b and move the least-significant 32 bits of the result to destination.

Q1 Core actions

• destination = (a * b) & 0xFFFFFFFF (Unsigned)

ALU flags

• ZF: Set if result is zero.

• NF: Set if result is negative.

• CF: 0.

• OF: 0.

• Functionally identical to muls32l.

mulu32h

Unsigned 32-bit Multiply High

variants

signature	mulu32h a: R , b: R , dst: R
arguments	a R0 to R63 b R0 to R63 dst R0 to R63
Q1 core runtime	20

signature	mulu32h a: R , rgt: I , dst: R
arguments	a R0 to R63 rgt \([0, 2^{32}-1]\) dst R0 to R63
Q1 core runtime	20

signature	mulu32h rgt: I , a: R , dst: R
arguments	rgt \([0, 2^{32}-1]\) a R0 to R63 dst R0 to R63
Q1 core runtime	20

Description

Multiply two unsigned 32-bit integers a and b and move the most-significant 32 bits of the result to destination.

Q1 Core actions

• destination = (a * b) >> 32 (Unsigned)

ALU flags

• ZF: Set if result is zero.

• NF: Set if result is negative.

• CF: 0.

• OF: 0.

muls32

Signed 32-bit Multiply

variants

signature	muls32 a: R , b: R , dst: R , dst: R
arguments	a R0 to R63 b R0 to R63 dst R0 to R63
Q1 core runtime	24

signature	muls32 a: R , rgt: I , dst: R , dst: R
arguments	a R0 to R63 rgt \([-2^{31}, 2^{31}-1]\) dst R0 to R63
Q1 core runtime	24

signature	muls32 rgt: I , a: R , dst: R , dst: R
arguments	rgt \([-2^{31}, 2^{31}-1]\) a R0 to R63 dst R0 to R63
Q1 core runtime	24

Description

Multiply two signed 32-bit integers, producing a 64-bit signed result stored across two destination registers.

Q1 Core actions

• {dest_msb, dest_lsb} = a * b (Signed)

ALU flags

• ZF: Set if result is zero.

• NF: Set if result is negative.

• CF: 0.

• OF: 0.

muls32l

Signed 32-bit Multiply Low

variants

signature	muls32l a: R , b: R , dst: R
arguments	a R0 to R63 b R0 to R63 dst R0 to R63
Q1 core runtime	20

signature	muls32l a: R , rgt: I , dst: R
arguments	a R0 to R63 rgt \([-2^{31}, 2^{31}-1]\) dst R0 to R63
Q1 core runtime	20

signature	muls32l rgt: I , a: R , dst: R
arguments	rgt \([-2^{31}, 2^{31}-1]\) a R0 to R63 dst R0 to R63
Q1 core runtime	20

Description

Multiply two signed 32-bit integers a and b and move the least-significant 32 bits of the result to destination.

Q1 Core actions

• destination = (a * b) & 0xFFFFFFFF (Signed)

ALU flags

• ZF: Set if result is zero.

• NF: Set if result is negative.

• CF: 0.

• OF: 0.

• Functionally identical to mulu32l.

muls32h

Signed 32-bit Multiply High

variants

signature	muls32h a: R , b: R , dst: R
arguments	a R0 to R63 b R0 to R63 dst R0 to R63
Q1 core runtime	20

signature	muls32h a: R , rgt: I , dst: R
arguments	a R0 to R63 rgt \([-2^{31}, 2^{31}-1]\) dst R0 to R63
Q1 core runtime	20

signature	muls32h rgt: I , a: R , dst: R
arguments	rgt \([-2^{31}, 2^{31}-1]\) a R0 to R63 dst R0 to R63
Q1 core runtime	20

Description

Multiply two signed 32-bit integers a and b and move the most-significant 32 bits of the result to destination.

Q1 Core actions

• destination = (a * b) >> 32 (Signed)

ALU flags

• ZF: Set if result is zero.

• NF: Set if result is negative.

• CF: 0.

• OF: 0.

and

Bitwise AND

variants

signature	and a: R , b: R , dst: R
arguments	a R0 to R63 b R0 to R63 dst R0 to R63
Q1 core runtime	12

signature	and a: R , b: I , dst: R
arguments	a R0 to R63 b \([-2^{31}, 2^{32}-1]\) dst R0 to R63
Q1 core runtime	12

signature	and b: I , a: R , dst: R
arguments	b \([-2^{31}, 2^{32}-1]\) a R0 to R63 dst R0 to R63
Q1 core runtime	12

Description

Perform a bitwise AND on a and b and move the result to destination.

Q1 Core actions

• destination = a & b

ALU flags

• ZF: Set if result is zero.

• NF: Set if result is negative.

• CF: 0.

• OF: 0.

test

Test Bits

variants

signature	test a: R , b: R
arguments	a R0 to R63 b R0 to R63
Q1 core runtime	12

signature	test a: R , b: I
arguments	a R0 to R63 b \([-2^{31}, 2^{32}-1]\)
Q1 core runtime	12

signature	test b: I , a: R
arguments	b \([-2^{31}, 2^{32}-1]\) a R0 to R63
Q1 core runtime	12

Description

Perform a bitwise AND on a and b without storing the result. Used to check specific bits via ALU flags.

Note

For example, test 4, R0 followed by jz @address can be used to jump to an address if the second bit if R0 is set.

Q1 Core actions

• a & b (result discarded)

ALU flags

• Same as and.

or

Bitwise OR

variants

signature	or a: R , b: R , dst: R
arguments	a R0 to R63 b R0 to R63 dst R0 to R63
Q1 core runtime	12

signature	or a: R , b: I , dst: R
arguments	a R0 to R63 b \([-2^{31}, 2^{32}-1]\) dst R0 to R63
Q1 core runtime	12

signature	or b: I , a: R , dst: R
arguments	b \([-2^{31}, 2^{32}-1]\) a R0 to R63 dst R0 to R63
Q1 core runtime	12

Description

Perform a bitwise OR on a and b and move the result to destination.

Q1 Core actions

• destination = a | b

ALU flags

• ZF: Set if result is zero.

• NF: Set if result is negative.

• CF: 0.

• OF: 0.

xor

Bitwise XOR

variants

signature	xor a: R , b: R , dst: R
arguments	a R0 to R63 b R0 to R63 dst R0 to R63
Q1 core runtime	12

signature	xor a: R , b: I , dst: R
arguments	a R0 to R63 b \([-2^{31}, 2^{32}-1]\) dst R0 to R63
Q1 core runtime	12

signature	xor b: I , a: R , dst: R
arguments	b \([-2^{31}, 2^{32}-1]\) a R0 to R63 dst R0 to R63
Q1 core runtime	12

Description

Perform a bitwise XOR on a and b and move the result to destination.

Q1 Core actions

• destination = a ^ b

ALU flags

• ZF: Set if result is zero.

• NF: Set if result is negative.

• CF: 0.

• OF: 0.

asl

Arithmetic Shift Left

variants

signature	asl a: R , b: R , dst: R
arguments	a R0 to R63 b R0 to R63 dst R0 to R63
Q1 core runtime	12

signature	asl a: R , rgt: I , dst: R
arguments	a R0 to R63 rgt \([0, 2^{32}-1]\) dst R0 to R63
Q1 core runtime	12

signature	asl rgt: I , a: R , dst: R
arguments	rgt \([-2^{31}, 2^{31}-1]\) a R0 to R63 dst R0 to R63
Q1 core runtime	12

Description

Shift a left by b bits. This is functionally identical to a logical left shift (lsl).

Q1 Core actions

• destination = a << b

ALU flags

• ZF: Set if result is zero.

• NF: Set if result is negative.

• CF: Last bit shifted out.

• OF: Set if bit shifted out is not equal to the sign bit.

asr

Arithmetic Shift Right

variants

signature	asr a: R , b: R , dst: R
arguments	a R0 to R63 b R0 to R63 dst R0 to R63
Q1 core runtime	12

signature	asr a: R , rgt: I , dst: R
arguments	a R0 to R63 rgt \([0, 2^{32}-1]\) dst R0 to R63
Q1 core runtime	12

signature	asr rgt: I , a: R , dst: R
arguments	rgt \([-2^{31}, 2^{31}-1]\) a R0 to R63 dst R0 to R63
Q1 core runtime	12

Description

Shift a right by b bits while preserving the sign bit.

Q1 Core actions

• destination = a >>> b (Sign-extended)

ALU flags

• ZF: Set if result is zero.

• NF: Set if result is negative.

• CF: Last bit shifted out.

• OF: 0.

lsr

Logical Shift Right

variants

signature	lsr a: R , b: R , dst: R
arguments	a R0 to R63 b R0 to R63 dst R0 to R63
Q1 core runtime	12

signature	lsr a: R , rgt: I , dst: R
arguments	a R0 to R63 rgt \([0, 2^{32}-1]\) dst R0 to R63
Q1 core runtime	12

signature	lsr rgt: I , a: R , dst: R
arguments	rgt \([0, 2^{32}-1]\) a R0 to R63 dst R0 to R63
Q1 core runtime	12

Description

Shift a right by b bits, padding with zeros.

Q1 Core actions

• destination = a >> b (Zero-extended)

ALU flags

• ZF: Set if result is zero.

• NF: Set if result is negative.

• CF: Last bit shifted out.

• OF: 0.

lsl

Logical Left Shift

variants

signature	lsl a: R , b: R , dst: R
arguments	a R0 to R63 b R0 to R63 dst R0 to R63
Q1 core runtime	12

signature	lsl a: R , rgt: I , dst: R
arguments	a R0 to R63 rgt \([0, 2^{32}-1]\) dst R0 to R63
Q1 core runtime	12

signature	lsl rgt: I , a: R , dst: R
arguments	rgt \([0, 2^{32}-1]\) a R0 to R63 dst R0 to R63
Q1 core runtime	12

Description

Shift a left by b bits. This is functionally identical to an arithmetic left shift (asl).

Q1 Core actions

• destination = a << b

ALU flags

• ZF: Set if result is zero.

• NF: Set if result is negative.

• CF: Last bit shifted out.

• OF: Set if bit shifted out is not equal to the sign bit.

Latched Instructions

set_mrk

Set Markers

variants

signature	set_mrk mrk: R
arguments	mrk R0 to R63
Q1 core runtime	4

signature	set_mrk mrk: I
arguments	mrk \([0, 2^{4}-1]\)
Q1 core runtime	4

Description

Set marker output channels to mask (bits 0–3), where the bit indices mean:

Module	bit3	bit 2	bit 1	bit 0
QCM	M4	M3	M2	M1
QRM	M4	M3	M2	M1
QCM-RF	M2	M1	O2	O1
QRM-RF	M2	M1	O	N/A
QRC	N/A	N/A	N/A	M0

Q1 Core actions

Set the mrk latched register.

RT Core actions

When the associated real-time instruction is executed, the marker bits are dispatched to the output logic.

Signal Path actions

• OR the value with those of other sequencers.

• Update the physical marker outputs and/or output switches to the state defined by the latched mask.

set_awg_gain

Set AWG Gain

variants

signature	set_awg_gain gain0: R , gain1: R
arguments	gain0 R0 to R63 gain1 R0 to R63
Q1 core runtime	4

signature	set_awg_gain gain0: I , gain1: I
arguments	gain0 \([-2^{15}, 2^{15}-1]\) gain1 \([-2^{15}, 2^{15}-1]\)
Q1 core runtime	4

Description

Sets the signal gain for the two AWG paths.

Q1 Core actions

Set the gain0 and gain1 latched registers. The values are integers ranging from -32,768 to 32,767.

When a latch-updating real-time instruction is executed, these values are sent to the RT-queue.

RT Core actions

When the associated real-time instruction is executed by the RT-core, the gain values are sent to the signal path.

Signal Path actions

Apply the gain factor to the waveform data on path 0 and path 1.

set_awg_offs

Set AWG Offset

variants

signature	set_awg_offs offs0: R , offs1: R
arguments	offs0 R0 to R63 offs1 R0 to R63
Q1 core runtime	4

signature	set_awg_offs offs0: I , offs1: I
arguments	offs0 \([-2^{15}, 2^{15}-1]\) offs1 \([-2^{15}, 2^{15}-1]\)
Q1 core runtime	4

Description

Sets the signal offset for the two AWG paths.

Q1 Core actions

Set the offset0 and offset1 latched registers. The values are integers ranging from -32,768 to 32,767.

These values are buffered until a latch-updating real-time instruction is sent to the RT-queue.

RT Core actions

When the associated real-time instruction is executed by the RT-core, the offset values are dispatched to the signal path.

Signal Path actions

Add the offset before the NCO to the signal on path 0 and path 1.

set_freq

Set Frequency

variants

signature	set_freq nco: R
arguments	nco R0 to R63
Q1 core runtime	4

signature	set_freq nco: I
arguments	nco \([-2^{31}, 2^{31}-1]\)
Q1 core runtime	4

Description

Sets the NCO frequency. The frequency is set using an integer in the range [\(-2\times 10^9, 2\times 10^9\)], which corresponds to a frequency range of [\(-500, 500\) MHz]. This provides \(4 \times 10^9\) discrete steps, where 1 MHz is represented by the integer \(4\times 10^6\).

Q1 Core actions

Set the freq latched register to nco.

When a latch updating real-time instruction is executed by the Q1 core, the freq latched register value is sent along with the real-time instruction to the RT-queue.

RT Core actions

When a latch updating real-time instruction is executed by the RT-core, the freq value that was latched to the instruction is sent to the relevant part of the signal path.

Signal Path actions

Update the NCO frequency to the value supplied by the RT-core.

reset_ph

Reset Phase

variants

signature	reset_ph
arguments	N/A
Q1 core runtime	4

Description

Resets the NCO’s accumulated phase to zero by setting \(t' \rightarrow 0\), \(\Phi \rightarrow 0\) and \(\phi \rightarrow 0\).

Q1 Core actions

Set the phase reset flag in the latched registers. This flag is sent to the RT-queue with the next latch-updating real-time instruction.

RT Core actions

When the associated real-time instruction is executed, a phase reset signal is sent to the NCO.

Signal Path actions

Reset the NCO phase accumulator, phase offset, and accumulated phase.

set_ph

Set Phase

variants

signature	set_ph nco: R
arguments	nco R0 to R63
Q1 core runtime	4

signature	set_ph nco: I
arguments	nco \((0, 1000000000)\)
Q1 core runtime	4

Description

Sets the NCO phase offset \(\phi\) to value.

Q1 Core actions

Set the phase latched register. The phase is set using an integer that maps a full \(360^\circ\) circle to an integer between 0 and \(10^9\) (e.g., \(45^\circ = 125 \times 10^6\)).

This value is buffered and sent to the RT-queue with the next latch-updating real-time instruction.

RT Core actions

When the associated real-time instruction is executed, the phase value is dispatched to the NCO.

Signal Path actions

Set the NCO phase offset to the supplied value.

set_ph_delta

Set Phase Delta

variants

signature	set_ph_delta nco: R
arguments	nco R0 to R63
Q1 core runtime	4

signature	set_ph_delta nco: I
arguments	nco \((0, 1000000000)\)
Q1 core runtime	4

Description

Adds an instantaneous phase kick (\(\Delta\phi\)) to the NCO’s total phase (\(t' \rightarrow t' + \delta\phi / (2\pi f)\)).

Q1 Core actions

Set the phase_delta latched register. This value is buffered and sent to the RT-queue with the next latch-updating real-time instruction.

RT Core actions

When the associated real-time instruction is executed, the phase_delta value is sent to the NCO.

Signal Path actions

Apply the dynamic phase shift to the NCO’s total phase.

set_cond

Set Conditional

variants

signature	set_cond cond: R , mask: R , op: R , else: I
arguments	cond R0 to R63 mask R0 to R63 op R0 to R63 else \([0, 2^{16}-1]\)
Q1 core runtime	4

signature	set_cond cond: I , mask: I , op: I , else: I
arguments	cond \([0, 2^{1}-1]\) mask \([0, 2^{15}-1]\) op \([0, 2^{3}-1]\) else \([0, 2^{16}-1]\)
Q1 core runtime	4

Description

Configures the condition for following RT instructions based on the trigger network. See this section for more details.

Q1 Core actions

Set the enable, mask, and operator latched registers.

RT Core actions

When the next real-time instruction is executed, the RT-core checks the condition. If true, the instruction executes; otherwise, it waits for else_duration ns.

set_digital

Set Digital Output

variants

signature	set_digital out: R , out: I , fine: R
arguments	out \([0, 2^{8}-1]\) fine R0 to R63
Q1 core runtime	4

signature	set_digital out: I , out: I , fine: I
arguments	out \([0, 2^{8}-1]\) fine \([0, 2^{11}-1]\)
Q1 core runtime	4

Description

Set the digital output of the sequencer/channel to high or low.

Q1 Core actions

Set the enable, mask, and fine_delay latched registers. Note that mask should always be set to 1.

RT Core actions

When the associated real-time instruction is executed, these values are sent to the digital output module.

Signal Path actions

Update the digital output state with a fine resolution (multiple of 1/128 ns, hardware resolution of 39 ps).

set_time_ref

Set Time Reference

variants

signature	set_time_ref
arguments	N/A
Q1 core runtime	4

Description

Configure the reference timestamp to the current sequencer time.

Q1 Core actions

Set the time reference flag in the latched registers.

RT Core actions

The current sequencer time is used as the timestamp reference for subsequent acquire_timetags commands.

set_scope_en

Set Scope Enable

variants

signature	set_scope_en scope: R
arguments	scope R0 to R63
Q1 core runtime	4

signature	set_scope_en scope: I
arguments	scope \([0, 2^{1}-1]\)
Q1 core runtime	4

Description

Trigger scope/trace acquisition by subsequent acquisition instructions.

Q1 Core actions

Set the enable flag in the latched registers (set enable = 1 to trigger).

RT Core actions

When the associated real-time instruction is executed, the scope enable state is updated.

Signal Path actions

Enable or disable scope/trace acquisition for the sequencer.

LINQ Feedback Instructions

The LINQ-based feedback architecture allows sequencers to share data in real-time within the cluster. For more details, see the LINQ-based feedback user guide.

Readout Feedback Instructions

fb_acq_tb_id

Thresholded Bit ID

variants

signature	fb_acq_tb_id fb: R , duration: I
arguments	fb R0 to R63 duration \([0, 2^{16}-1]\)
Q1 core runtime	4

signature	fb_acq_tb_id fb: I , duration: I
arguments	fb \([0, 2^{8}-1]\) duration \([0, 2^{16}-1]\)
Q1 core runtime	4

Description

Configures the tag id attached to thresholded bits (TB) sent over LINQ and waits duration ns.

Note

TB are transmitted at the end of the acquisition window in 2-bit format (data bit + valid bit set to 1). If id = 0, transmission is disabled.

Q1 Core actions

• Send the id and duration to the RT-queue.

RT Core actions

• Configure the LINQ output to tag thresholded bits with id.

• Wait for duration ns.

fb_acq_tb_cfg

Thresholded Bit Config

variants

signature	fb_acq_tb_cfg fb: R , duration: I
arguments	fb R0 to R63 duration \([0, 2^{16}-1]\)
Q1 core runtime	4

signature	fb_acq_tb_cfg fb: I , fb: I , fb: I , duration: I
arguments	fb \([0, 2^{7}-1]\) duration \([0, 2^{16}-1]\)
Q1 core runtime	4

Description

The write_combine flag (wc) enables (1) or disables (0) write-combine mode. bit_pos defines the starting bit position for this sequencer’s TB in the shared payload, length specifies the total payload size in bytes, and the real-time queue waits duration ns after configuration.

Q1 Core actions

• Send configuration parameters to the RT-queue.

RT Core actions

• Update write-combine configuration for thresholded bits.

• Wait for duration ns.

fb_acq_tb_valid

Thresholded Bit Valid

variants

signature	fb_acq_tb_valid fb: R , duration: I
arguments	fb R0 to R63 duration \([0, 2^{16}-1]\)
Q1 core runtime	4

signature	fb_acq_tb_valid fb: I , duration: I
arguments	fb \([0, 2^{1}-1]\) duration \([0, 2^{16}-1]\)
Q1 core runtime	4

Description

Configures the valid bit for thresholded bits (TB) sent over LINQ and waits duration ns. Default value for the valid bit is 1.

Q1 Core actions

• Send the valid bit and duration to the RT-queue.

RT Core actions

• Update the valid bit for subsequent TB transmissions.

• Wait for duration ns.

fb_acq_tb_extra

Thresholded Bit Extra

variants

signature	fb_acq_tb_extra fb: R , duration: I
arguments	fb R0 to R63 duration \([0, 2^{16}-1]\)
Q1 core runtime	4

signature	fb_acq_tb_extra fb: I , fb: I , duration: I
arguments	fb \([0, 2^{16}-1]\) duration \([0, 2^{16}-1]\)
Q1 core runtime	4

Description

The enable flag (enable) enables (1) or disables (0) inclusion of extra bytes in the sequencer’s TB payload.

Q1 Core actions

• Send the enable, extra value, and duration to the RT-queue.

RT Core actions

• Update the extra data configuration for TB.

• Wait for duration ns.

fb_acq_tb_mock

Thresholded Bit Mock

variants

signature	fb_acq_tb_mock fb: R , duration: I
arguments	fb R0 to R63 duration \([0, 2^{16}-1]\)
Q1 core runtime	4

signature	fb_acq_tb_mock fb: I , fb: I , fb: I , duration: I
arguments	fb \([0, 2^{1}-1]\) duration \([0, 2^{16}-1]\)
Q1 core runtime	4

Description

Enables transmission of mock thresholded bits instead of real TB data when enable = 1. valid sets the valid bit, data sets the TB value, and count specifies the number of samples to send.

Q1 Core actions

• Send mock data parameters to the RT-queue.

RT Core actions

• Enable/disable and configure mock TB transmission.

fb_acq_iq_id

IQ ID

variants

signature	fb_acq_iq_id fb: R , duration: I
arguments	fb R0 to R63 duration \([0, 2^{16}-1]\)
Q1 core runtime	4

signature	fb_acq_iq_id fb: I , duration: I
arguments	fb \([0, 2^{8}-1]\) duration \([0, 2^{16}-1]\)
Q1 core runtime	4

Description

Configures the tag id attached to IQ data sent over LINQ and waits duration ns.

Note

IQ values are transmitted at the end of the acquisition window as two consecutive words (I followed by Q). If id = 0, transmission is disabled.

Q1 Core actions

• Send the id and duration to the RT-queue.

RT Core actions

• Configure the LINQ output to tag IQ data with id.

• Wait for duration ns.

fb_acq_iq_shift

IQ Shift

variants

signature	fb_acq_iq_shift fb: R , duration: I
arguments	fb R0 to R63 duration \([0, 2^{16}-1]\)
Q1 core runtime	4

signature	fb_acq_iq_shift fb: I , duration: I
arguments	fb \([0, 2^{6}-1]\) duration \([0, 2^{16}-1]\)
Q1 core runtime	4

Description

Right-shifts IQ values by shift bits before transmission to reduce resolution. For example, a shift of 8 transmits the upper 24 bits, discarding the 8 least-significant bits. The real-time queue waits duration ns after configuration.

Q1 Core actions

• Send the shift value and duration to the RT-queue.

RT Core actions

• Update the IQ shift configuration.

• Wait for duration ns.

Time-tag Feedback Instructions

fb_llp_tags_id

Low-latency Time-tags ID

variants

signature	fb_llp_tags_id fb: R , duration: I
arguments	fb R0 to R63 duration \([0, 2^{16}-1]\)
Q1 core runtime	4

signature	fb_llp_tags_id fb: I , duration: I
arguments	fb \([0, 2^{8}-1]\) duration \([0, 2^{16}-1]\)
Q1 core runtime	4

Description

Configures the tag id attached to low-latency time-tags sent over LINQ and waits duration ns.

Note

Detected time-tags are streamed in real time with 1 ns resolution while the acquisition window remains open. If id = 0, transmission is disabled.

Q1 Core actions

• Send the id and duration to the RT-queue.

RT Core actions

• Configure the LINQ output to tag low-latency time-tags with id.

• Wait for duration ns.

fb_llp_ttls_id

Low-latency TTL Counts ID

variants

signature	fb_llp_ttls_id fb: R , duration: I
arguments	fb R0 to R63 duration \([0, 2^{16}-1]\)
Q1 core runtime	4

signature	fb_llp_ttls_id fb: I , duration: I
arguments	fb \([0, 2^{8}-1]\) duration \([0, 2^{16}-1]\)
Q1 core runtime	4

Description

Configures the tag id attached to low-latency TTL counts sent over LINQ and waits duration ns.

Note

The number of detected photon events above the configured threshold is transmitted at the end of the acquisition window. If id = 0, transmission is disabled.

Q1 Core actions

• Send the id and duration to the RT-queue.

RT Core actions

• Configure the LINQ output to tag low-latency TTL counts with id.

• Wait for duration ns.

fb_tdc_tags_id

High-resolution Time-tags ID

variants

signature	fb_tdc_tags_id fb: R , duration: I
arguments	fb R0 to R63 duration \([0, 2^{16}-1]\)
Q1 core runtime	4

signature	fb_tdc_tags_id fb: I , duration: I
arguments	fb \([0, 2^{8}-1]\) duration \([0, 2^{16}-1]\)
Q1 core runtime	4

Description

Configures the tag id attached to high-resolution time-tags sent over LINQ and waits duration ns.

Note

Time-tags are generated with approximately 8 ps resolution and are transmitted after additional processing latency. If id = 0, transmission is disabled.

Q1 Core actions

• Send the id and duration to the RT-queue.

RT Core actions

• Configure the LINQ output to tag high-resolution time-tags with id.

• Wait for duration ns.

fb_tdc_tdelta_id

Time Delta ID

variants

signature	fb_tdc_tdelta_id fb: R , duration: I
arguments	fb R0 to R63 duration \([0, 2^{16}-1]\)
Q1 core runtime	4

signature	fb_tdc_tdelta_id fb: I , duration: I
arguments	fb \([0, 2^{8}-1]\) duration \([0, 2^{16}-1]\)
Q1 core runtime	4

Description

Configures the tag id attached to the time difference between two detected events and waits duration ns.

Note

The time delta is computed between a configured reference channel and source channel (which may be the same) with 1/128 ns resolution and ±16.7 ms range. If id = 0, transmission is disabled.

Q1 Core actions

• Send the id and duration to the RT-queue.

RT Core actions

• Configure the LINQ output to tag time delta data with id.

• Wait for duration ns.

Common Feedback Instructions

fb_com_data

Send Common Data

variants

signature	fb_com_data fb: I , fb: R , duration: I
arguments	fb R0 to R63 duration \([0, 2^{16}-1]\)
Q1 core runtime	4

signature	fb_com_data fb: I , fb: I , duration: I
arguments	fb \([0, 2^{32}-1]\) duration \([0, 2^{16}-1]\)
Q1 core runtime	4

Description

Send an immediate or register value with the specified id over LINQ and wait duration ns.

Q1 Core actions

• Send the id, value, and duration to the RT-queue.

RT Core actions

• Transmit the data value over LINQ with the specified id.

• Wait for duration ns.

fb_cmd

Feedback Command

variants

signature	fb_cmd fb: I , fb: R , duration: I
arguments	fb R0 to R63 duration \([0, 2^{16}-1]\)
Q1 core runtime	4

signature	fb_cmd fb: I , fb: I , duration: I
arguments	fb \([0, 2^{32}-1]\) duration \([0, 2^{16}-1]\)
Q1 core runtime	4

Description

Send a command value (register) with the specified id over LINQ and wait duration ns.

Q1 Core actions

• Send the id, value, and duration to the RT-queue.

RT Core actions

• Transmit the command value over LINQ with the specified id.

• Wait for duration ns.

fb_com_cfg

Common Data Config

variants

signature	fb_com_cfg fb: R , duration: I
arguments	fb R0 to R63 duration \([0, 2^{16}-1]\)
Q1 core runtime	4

signature	fb_com_cfg fb: I , fb: I , fb: I , duration: I
arguments	fb \([0, 2^{7}-1]\) duration \([0, 2^{16}-1]\)
Q1 core runtime	4

Description

Configure write-combine mode for common data transmissions.

Q1 Core actions

• Send configuration parameters to the RT-queue.

RT Core actions

• Update write-combine configuration for common data.

• Wait for duration ns.

fb_com_extra

Common Data Extra

variants

signature	fb_com_extra fb: R , duration: I
arguments	fb R0 to R63 duration \([0, 2^{16}-1]\)
Q1 core runtime	4

signature	fb_com_extra fb: I , fb: I , duration: I
arguments	fb \([0, 2^{16}-1]\) duration \([0, 2^{16}-1]\)
Q1 core runtime	4

Description

Include extra bytes in the common data payload.

Q1 Core actions

• Send the enable, extra value, and duration to the RT-queue.

RT Core actions

• Update the extra data configuration for common data.

• Wait for duration ns.

fb_pop_data

Pop Data

variants

signature	fb_pop_data fb: I , fb: R
arguments	fb R0 to R63
Q1 core runtime	4

Description

Pop a data value from the feedback queue with the specified id and store it in destination.

Q1 Core actions

• Pop data from the feedback queue with id.

• Store the result in destination.

fb_pull_data

Pull Data

variants

signature	fb_pull_data fb: R , fb: R
arguments	fb R0 to R63
Q1 core runtime	4

Description

Pull a data value from the feedback queue using an id stored in a register and store it in destination.

Q1 Core actions

• Pull data from the feedback queue using the id in the source register.

• Store the result in destination.

Real-time Instructions

wait

Wait

variants

signature	wait duration: R
arguments	duration R0 to R63
Q1 core runtime	4

signature	wait duration: I
arguments	duration \([0, 2^{16}-1]\)
Q1 core runtime	4

Description

Wait for the specified duration without performing any signal path actions.

Q1 Core actions

• Send a wait to the RT-queue with arguments.

RT Core actions

• Wait for duration ns.

wait_sync

Wait for synchronization

variants

signature	wait_sync duration: R
arguments	duration R0 to R63
Q1 core runtime	4

signature	wait_sync duration: I
arguments	duration \([0, 2^{16}-1]\)
Q1 core runtime	4

Description

Wait for a synchronization pulse from the central controller.

Q1 Core actions

• Send a wait_sync to the RT-queue.

RT Core actions

• Wait for the synchronization pulse.

• Wait for duration ns.

wait_trigger

Wait for trigger

variants

signature	wait_trigger trig: R , duration: R
arguments	trig R0 to R63 duration R0 to R63
Q1 core runtime	4

signature	wait_trigger trig: I , duration: I
arguments	trig \([0, 2^{4}-1]\) duration \([0, 2^{16}-1]\)
Q1 core runtime	4

Description

Wait for a trigger on the trigger network at the specified address.

Q1 Core actions

• Send a wait_trigger to the RT-queue with arguments.

RT Core actions

• Wait for a trigger on the trigger network address.

• Wait for duration ns.

play

Play Waveforms

variants

signature	play wave0: R , wave1: R , duration: I
arguments	wave0 R0 to R63 wave1 R0 to R63 duration \([0, 2^{16}-1]\)
Q1 core runtime	4

signature	play wave0: I , wave1: I , duration: I
arguments	wave0 \([0, 2^{10}-1]\) wave1 \([0, 2^{10}-1]\) duration \([0, 2^{16}-1]\)
Q1 core runtime	4

Description

Play waveforms on the sequencer paths.

Q1 Core actions

• Send a play to the RT-queue with the arguments and latched registers.

RT Core actions

• Send all latched registers to the relevant parts of the signal path.

• Send a play with arguments to the signal path.

• Wait for duration ns.

Signal Path actions

Start playing the wave referred to by wave0 on path_0 and wave1 on path_1.

acquire

Acquisition

variants

signature	acquire acq: I , bin: R , duration: I
arguments	acq \([0, 2^{5}-1]\) bin R0 to R63 duration \([0, 2^{16}-1]\)
Q1 core runtime	4

signature	acquire acq: I , bin: I , duration: I
arguments	acq \([0, 2^{5}-1]\) bin \([0, 2^{24}-1]\) duration \([0, 2^{16}-1]\)
Q1 core runtime	4

Description

Acquire data into the specified acquisition index and bin.

Q1 Core actions

• Send an acquire to the RT-queue with arguments and latched registers.

RT Core actions

• Send all latched registers to the relevant parts of the signal path.

• Send an acquire with arguments to the signal path.

• Wait for duration ns.

Signal Path actions

• Acquire the signal from the demodulation path into the bin of the acquisition index.

• Send the thresholded bit to the trigger network on the relevant address if thresholded_acq_trigger_en and thresholded_acq_trigger_address are set.

• Send a LINQ message according to the relevant fb_acq_.... commands.

acquire_weighted

Weighted Acquisition

variants

signature	acquire_weighted acq: I , bin: R , weight: R , weight: R , duration: I
arguments	acq \([0, 2^{5}-1]\) bin R0 to R63 weight R0 to R63 duration \([0, 2^{16}-1]\)
Q1 core runtime	4

signature	acquire_weighted acq: I , bin: I , weight: I , weight: I , duration: I
arguments	acq \([0, 2^{5}-1]\) bin \([0, 2^{24}-1]\) weight \([0, 2^{6}-1]\) duration \([0, 2^{16}-1]\)
Q1 core runtime	4

Description

Acquire data using custom integration weights.

Q1 Core actions

• Send an acquire_weighted to the RT-queue with arguments and latched registers.

RT Core actions

• Send all latched registers to the relevant parts of the signal path.

• Send an acquire_weighted with arguments to the signal path.

• Wait for duration ns.

Signal Path actions

• Acquire the signal from the demodulation path using integration weights weight0 and weight1 into the bin of the acquisition index.

• Send the thresholded bit to the trigger network on the relevant address if thresholded_acq_trigger_en and thresholded_acq_trigger_address are set.

• Send a LINQ message according to the relevant fb_acq_.... commands.

acquire_ttl

TTL Acquisition

variants

signature	acquire_ttl acq: I , bin: R , ttl: I , duration: I
arguments	acq \([0, 2^{5}-1]\) bin R0 to R63 ttl \([0, 2^{1}-1]\) duration \([0, 2^{16}-1]\)
Q1 core runtime	4

signature	acquire_ttl acq: I , bin: I , ttl: I , duration: I
arguments	acq \([0, 2^{5}-1]\) bin \([0, 2^{24}-1]\) ttl \([0, 2^{1}-1]\) duration \([0, 2^{16}-1]\)
Q1 core runtime	4

Description

Perform a TTL (thresholded) acquisition.

Q1 Core actions

• Send an acquire_ttl to the RT-queue with arguments and latched registers.

RT Core actions

• Send all latched registers to the relevant parts of the signal path.

• Send an acquire_ttl with arguments to the signal path.

• Wait for duration ns.

Signal Path actions

If the parameter enable is set, start acquiring signal from the TTL acquisition into the bin of the acquisition index. Then, everytime the threshold is crossed,

• Add 1 to the bin value.

• If ttl_acq_auto_bin_incr_en is set, increment the bin.

• Send the thresholded bit to the trigger network based on TTL acquisition settings.

If the parameter enable is not set, stop acquiring signal.

acquire_timetags

Timetag Acquisition

variants

signature	acquire_timetags acq: I , bin: R , window: I , fine: R , duration: I
arguments	acq \([0, 2^{5}-1]\) bin R0 to R63 window \([0, 2^{1}-1]\) fine R0 to R63 duration \([0, 2^{16}-1]\)
Q1 core runtime	8

signature	acquire_timetags acq: I , bin: I , window: I , fine: I , duration: I
arguments	acq \([0, 2^{5}-1]\) bin \([0, 2^{24}-1]\) window \([0, 2^{1}-1]\) fine \([0, 2^{11}-1]\) duration \([0, 2^{16}-1]\)
Q1 core runtime	8

Description

Perform an acquisition to record arrival times of pulses (timetags).

Q1 Core actions

• Send all latched registers to the relevant parts of the signal path.

• Send an acquire_timetags to the RT-queue with arguments.

RT Core actions

• Send an acquire_timetags with arguments to the signal path.

• Wait for duration ns.

Signal Path actions

Record timestamps of pulses with a specific delay and enable configuration.

acquire_digital

Digital Acquisition

variants

signature	acquire_digital acq: I , bin: R , duration: I
arguments	acq \([0, 2^{5}-1]\) bin R0 to R63 duration \([0, 2^{16}-1]\)
Q1 core runtime	8

signature	acquire_digital acq: I , bin: I , duration: I
arguments	acq \([0, 2^{5}-1]\) bin \([0, 2^{24}-1]\) duration \([0, 2^{16}-1]\)
Q1 core runtime	8

Description

Perform a digital acquisition on the input.

Q1 Core actions

• Send an acquire_digital to the RT-queue with arguments.

RT Core actions

• Send all latched registers to the relevant parts of the signal path.

• Send an acquire_digital with arguments to the signal path.

• Wait for duration ns.

Signal Path actions

Perform digital sampling of the input signal into the specified bin.

upd_thres

Update Threshold

variants

signature	upd_thres dio: I , fb: R , duration: I
arguments	dio \([0, 2^{2}-1]\) fb R0 to R63 duration \([0, 2^{16}-1]\)
Q1 core runtime	8

signature	upd_thres dio: I , fb: I , duration: I
arguments	dio \([0, 2^{2}-1]\) fb \([0, 2^{32}-1]\) duration \([0, 2^{16}-1]\)
Q1 core runtime	8

Description

Update the threshold used for signal classification.

Q1 Core actions

• Send an upd_thres to the RT-queue with arguments.

RT Core actions

• Send an upd_thres with arguments to the signal path classification logic.

• Wait for duration ns.

Signal Path actions

• Send all latched registers to the relevant parts of the signal path.

• Update the classification threshold at index to value.

upd_param

Update Parameters

variants

signature	upd_param duration: R
arguments	duration R0 to R63
Q1 core runtime	4

signature	upd_param duration: I
arguments	duration \([0, 2^{16}-1]\)
Q1 core runtime	4

Description

Force an update of latched signal path parameters without a play or acquire command.

Q1 Core actions

• Send an upd_param to the RT-queue with the current latched registers.

RT Core actions

• Send all latched registers to the relevant parts of the signal path.

• Wait for duration ns.

latch_rst

Latch Reset

variants

signature	latch_rst duration: R
arguments	duration R0 to R63
Q1 core runtime	4

signature	latch_rst duration: I
arguments	duration \([0, 2^{16}-1]\)
Q1 core runtime	4

Description

Reset all trigger network address counters to 0.

Q1 Core actions

• Send a latch_rst to the RT-queue.

RT Core actions

• Send a latch_rst to the trigger network address counters.

• Wait for duration ns.

Signal Path actions

Set all trigger network address counters to 0.

set_latch_en

Set Latch Enable

variants

signature	set_latch_en latch: R , duration: I
arguments	latch R0 to R63 duration \([0, 2^{16}-1]\)
Q1 core runtime	4

signature	set_latch_en latch: I , duration: I
arguments	latch \([0, 2^{1}-1]\) duration \([0, 2^{16}-1]\)
Q1 core runtime	4

Description

Enable or disable the trigger latching mechanism.

Q1 Core actions

• Send a set_latch_en to the RT-queue.

RT Core actions

• Enable or disable the trigger latching based on enable.

• Wait for duration ns.